unisonic technologies co., ltd 4053 cmos ic www.unisonic.com.tw 1 of 7 copyright ? 2012 unisonic technologies co., ltd qw-r502-036.d triple 2-channel analog multiplexers/demultiplexers ? description utc 4053 is triple 2-channel analog multiplexers/demultiplexers for application as digitally?controlled analog switches. the device has three separate digital control inputs and an inhibit input. it feature low on impedance and very low off leakage current. control of analog signals up to the complete supply voltage range can be achieved. ? features * wide analog voltage range: v dd -v ee = 3v~18v. (note: v ee must be Q v ss ) * break-before-make switching eliminates channel overlap. * linearized transfer characteristics * implement an spdt switch effectively. * pin to pin replacement for cd4053 ? ordering information ordering number package packing lead free halogen free 4053l-d16-t 4053g-d16-t dip-16 tube 4053l-p16-r 4053g-p16-r tssop-16 tape reel 4053l-p16-t 4053g-p16-t tssop-16 tube 4053l-s16-r 4053g-s16-r sop-16 tape reel 4053L-S16-T 4053g-s16-t sop-16 tube
4053 cmos ic unisonic technologies co., ltd 2 of 7 www.unisonic.com.tw qw-r502-036.d ? pin configuration z1 y1 y0 z z0 inh vee vss x vdd y x1 x0 a b c utc 4053 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ? pin description pin no. symbal name and function 14,15,4 x,y,z commons input/output 6 inh inhibit input 7 v ee supply voltage 8 v ss ground 11,10,9 a,b,c digital control inputs 12,13 x0,x1 a-x swit ches inputs/outputs 2,1 y0,y1 b-y switches inputs/outputs 5,3 z0,z1 c-z switches inputs/outputs 16 v dd positive supply voltage
4053 cmos ic unisonic technologies co., ltd 3 of 7 www.unisonic.com.tw qw-r502-036.d ? absolute maximum rating parameter symbol ratings unit dc supply voltage (referenced to v ee , v ss R v ee ) v dd -0.5 ~ +18 v input or output voltage (dc or transient) (referenced to v ss for control inputs and v ee for switch i/o) v in , v out -0.5 ~ v dd +0.5 v input current (dc or transient), per control pin i in 10 ma switch through current i sw 25 ma power dissipation p d 500 mw derating above 65c 7 mw/c junction temperature t j 125 c operating temperature t opr -40 ~ +125 c storage temperature t stg -40 ~ +150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? electrical characteristics (t a =25c, unless otherwise specified.) parameter symbol test conditions min typ max unit supply requirements (voltages referenced to v ee ) power supply voltage range v dd v dd ? 3 R v ss R v ee 3 18 v quiescent current per package v dd =5v i q control inputs: v in = v ss or v dd switch i/o: v ee Q v i/o Q v dd , v sw Q 500mv (note 2) 0.005 5 a v dd =10v 0.010 10 a v dd =15v 0.015 20 a total supply current (dynamic plus quiescent, per package) v dd =5v i d(av) t a =25c only (the channel component, (v in -v out )/r on , is excluded) (0.07 a/khz) f + i q a v dd =10v (0.20 a/khz) f + i q a v dd =15v (0.36 a/khz) f + i q a switches in/out and commons out/in -- x, y, z (voltages referenced to v ee ) recommended peak?to?peak voltage into or out of the switch v i/o channel on or off 0 v dd v pp recommended static or dynamic voltage across the switch (note2) v sw channel on 0 600 mv output offset voltage v o ( off ) v in = 0v, no load 10 v on resistance v dd =5v r on v sw Q 500mv v in = v il or v ih (control), and v in = 0 to v dd (switch) 250 1050 ? v dd =10v 120 500 ? v dd =15v 80 280 ? on resistance between any two channels in the same package v dd =5v r on 25 70 ? v dd =10v 10 50 ? v dd =15v 10 45 ? off?channel leakage current i off v in = v il or v ih (control) channel to channel or any one channel, v dd =15v 0.05 100 na capacitance, switch i/o c i/o inhibit = v dd 10 pf capacitance, common o/i c o/i inhibit = v dd 17 pf capacitance, feedthrough (channel off) c i/o pins not adjacent 0.15 pf pins adjacent 0.47 pf control inputs ? inhibit a, b, c (voltages referenced to v ss ) low level input voltage v dd =5v v il r on = per spec, i off = per spec 2.25 1.5 v v dd =10v 4.50 3.0 v v dd =15v 6.75 4.0 v high level input voltage v dd =5v v ih r on = per spec, i off = per spec 3.5 2.75 v v dd =10v 7.0 5.50 v v dd =15v 11 8.25 v input leakage current i leak v in = 0 or v dd , v dd =15v 0.00001 0.1 a input capacitance c in 5.0 7.5 pf
4053 cmos ic unisonic technologies co., ltd 4 of 7 www.unisonic.com.tw qw-r502-036.d ? dynamic electrical characteristics (c l = 50pf, t a =25c, v ee Q v ss , unless otherwise specified) parameter symbol v dd -v ee v dc test conditions min typ max unit propagation delay times switch input to switch output (r l = 10 k ? ) t plh, t phl 5 t plh , t phl =(0.17 ns/pf)c l + 16.5ns 25 65 ns 10 t plh , t phl =(0.08 ns/pf)c l + 4.0ns 8.0 20 ns 15 t plh , t phl =(0.06 ns/pf)c l + 3.0ns 6.0 15 ns inhibit to output t phz, t plz t pzh, t pzl 5 (r l =10k ? , v ee =v ss ), output ?1? or ?0? to high impedance, or high impedance to ?1? or ?0? level 275 550 ns 10 140 280 ns 15 110 220 ns control input to output t plh, t phl 5 r l = 10k ? , v ee = v ss 300 600 ns 10 120 240 ns 15 80 160 ns total harmonic distortion thd 10 r l = 10k ? , f = 1 khz, v in = 5 v pp 0.07 % bandwidth bw 10 r l =1k ? , v in = 1/2(v dd -v ee ) p-p, c l =50pf, 20 log (v out /v in )= -3db) 17 mhz off channel feedthrough attenuation 10 r l =1k ? , v in = 1/2(v dd -v ee ) p-p f in = 55mhz -50 db channel separation 10 r l = 1k ? , v in = 1/2 v dd -v ee )p-p f in = 3mhz -50 db crosstalk, control input to common o/i 10 r 1 = 1k ? , r l = 10k ? control t tlh = t thl = 20ns, inhibit = v ss 75 mv note: 1. data of ?typ? is intended as an indi cation of the ic?s potential performance. 2. for voltage drops across the switch( v sw )>600mv (>300mv at high temperature), excessive v dd current may be drawn, i.e. the current out of the switch may contain both v dd and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded.
4053 cmos ic unisonic technologies co., ltd 5 of 7 www.unisonic.com.tw qw-r502-036.d ? test circuit v dd v ee v ee v dd v dd v dd out/in out/in in/out control in/out level converted control switch circuit schematic ? truth table control inputs on switches inhibit select c b a utc 4053 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 z0 y0 x0 z0 y0 x1 z0 y1 x0 z0 y1 x1 0 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 z1 y0 x0 z1 y0 x1 z1 y1 x0 z1 y1 x1 1 x x x none x = don?t care utc 4053 functional diagram v ee v dd 16 v ss 8 7 9 b 10 c a 11 6 inh level converter binary to 1 - of - 2 decoder with inhibit x0 12 x1 13 y0 2 y1 1 z0 5 z1 3 14 x 15 y 4 z
4053 cmos ic unisonic technologies co., ltd 6 of 7 www.unisonic.com.tw qw-r502-036.d ? typical characteristics "on" ( ? ) "on" resistance, r on ( ? ) resistance, r on -10 0 300 350 200 input voltage , v in (v) "on" resistance, r on ( ) 250 150 100 50 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10 v dd = 2.5 v v ee = - 2.5 v t a =25 c
4053 cmos ic unisonic technologies co., ltd 7 of 7 www.unisonic.com.tw qw-r502-036.d utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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